SRAM型FPGA单粒子翻转效应加固方法

姜昱光; 韩建伟; 朱翔; 蔡明辉

doi:10.13700/j.bh.1001-5965.2013.0514

SRAM型FPGA单粒子翻转效应加固方法

doi: 10.13700/j.bh.1001-5965.2013.0514

中国科学院空间科学与应用研究中心, 北京 100190

基金项目:

国家自然科学基金资助项目（40974113）；中国科学院知识创新工程青年基金资助项目（O82111A17S）；基础科研资助项目（A1320110028）；中国科学院支撑技术资助项目（110161501038）

详细信息

作者简介:
姜昱光（1986-），男，山东烟台人，博士生，jiangyuguang@nssc.ac.cn.

中图分类号: V524.3
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出版历程
- 收稿日期: 2013-09-04
- 网络出版日期: 2014-08-20

Single event upset mitigation testing of SRAM-based FPGAs

Center for Space Science and Applied Research, Chinese Academy of Sciences, Beijing 100190, China

摘要

摘要: 应用重离子加速器和皮秒脉冲激光器开展Virtex-Ⅱ FPGA（Field Programmable Gate Array）单粒子效应加固方法有效性研究.实验结果表明，同时应用三模冗余和动态刷新加固方法能够完全纠正单粒子效应产生的功能错误.实验获得数据加密算法在不同单粒子效应加固方法下功能错误截面，发现少量的存储位翻转就可以导致程序功能错误；程序功能对存储位翻转较敏感.分析Virtex-Ⅱ FPGA不同加固方法在不同卫星轨道的有效性，同时应用动态刷新和三模冗余加固方法，可以完全校正由于存储位翻转造成的功能错误.重离子加速器和脉冲激光器实验结果同时表明，脉冲激光可以模拟重离子加速器研究单粒子效应加固方法有效性.
- 三模冗余 /
- 动态刷新 /
- 脉冲激光 /
- 重离子 /
- 现场可编程门阵列
Abstract: Pulsed laser and heavy ions irradiation experiment was applied to study the effectiveness of the mitigation techniques of triple modular redundancy(TMR) and dynamic scrubbing for the Virtex-Ⅱ XC2V1000. When both dynamic scrubbing and TMR methods were used, the design of data encryption standard (DES) was observed to be essentially immune to functional errors. The cross section for functional errors utilizing different mitigation techniques was obtained, and the functional error was sensitive to configuration memory upsets. According to error rates of a Virtex-Ⅱ XC2V1000 in polar orbit for configuration memory, dynamic scrubbing in combination with TMR can repair the design to maintain state information, and the only effective mitigation method for an SRAM-based field programmable gate array (FPGA) design intended for space flight is to incorporate both TMR and scrubbing. The result shows that pulsed laser can be used to evaluate the mitigation techniques of TMR and dynamic scrubbing.
- triple modular redundancy /
- dynamic scrubbing /
- pulsed laser /
- heavy ions /
- field programmable gate array (FPGA)

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参考文献(15)

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