Fast reliability evaluation for SRAM-based spaceborne FPGAs
-
摘要: 空间辐射环境严重影响星载SRAM (Static Random Access Memory)型FPGA (Field Programmable Gate Array)的可靠性,提出了星载SRAM型FPGA可靠性快速验证评估方法.在传统故障注入验证的基础上,引入可靠性预评估技术,在逻辑门级分析单粒子翻转对FPGA配置信息位的影响,同时对TMR (Triple Modular Redundancy)冗余方式进行单粒子翻转关键位置评估.然后构成不同敏感级别的故障序列,最后根据应用需求选择不同故障序列进行故障注入从而有效快速评估系统可靠性.该方法与逐位翻转相比,能够在保证故障覆盖率的同时,有效地减少实验时间,提高实验效率.Abstract: Static random access memory(SRAM)-based field programmable gate arrays (FPGAs) reliability is seriously affected by space radiation. A new method for fast reliability evaluation of SRAM-based FPGAs was proposed. Based on traditional fault injection technique, a pre-evaluation was introduced to analyze the effect of single event upsets (SEU) in logic gate-level and SEU sensitive bits in triple modular redundancy (TMR). Then, the fault sequences of different sensitive level were formed. Finally, different fault sequences were selected depending on the application needs and injected into system for evaluating reliability. The method can not only reduce the experiment times and improve the experiment efficiency but also ensure the fault coverage.
-
Key words:
- spaceborne FPGA /
- fault injection /
- single event upset /
- reliability evaluation
-
[1] Kastensmidt F L,Neuberger G,Hentschke R F,et al.Designing fault-tolerant techniques for SRAM-Based FPGAs[J].IEEE Design and Test of Computers,2004,21(6):552-562 [2] Sterpone L,Battezzati N.A novel design flow for the performance optimization of fault tolerant circuits on SRAM-based FPGA's //Keymeulen D.Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems.Los Alamitos:IEEE Computer Society,2008:157-163 [3] 费尔南达·利马·卡斯腾斯密得,路易吉·卡罗,里卡多·赖斯.基于SRAM的FPGA容错技术[M].杨孟飞,龚健,文亮,等译.北京:中国宇航出版社,2009:28-30 Fernanda L K,Luigi C,Ricardo R.Fault-tolerance techniques for SRAM-based FPGAs[M].Translated by Yang Mengfei,Gong Jian,Wen Liang,et al.Beijing:China Astronautic Publishing House,2009:28-30(in Chinese) [4] Manuzzato A,Gerardin S,Paccagnella A,et al.Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumulation in commercial SRAM-based FPGAs[J].IEEE Transactions on Nuclear Science,2008,55(4):1968-1973 [5] Alderighi M,D-Angelo S,Mancini M,et al.A fault injection tool for SRAM-based FPGAs //Metra C.Proceedings of IEEE International On-Line Testing Symposium.Los Alamitos:IEEE Computer Society,2003:129-133 [6] Alderighi M,Casini F,D-Angelo S,et al.A tool for injecting SEU-like faults into the configuration control mechanism of Xilinx virtex FPGAs //Martin D C.Proceeding of IEEE International Symposium on Defect and Fault Tolerance in VLSI System.Los Alamitos:IEEE Computer Society,2003:71-78 [7] Clark J A,Pradhan D K.Fault injection:a method for validating computer system dependability[J].IEEE Computer,1995,28(6):47-55 [8] 宋凝芳,秦姣梅,潘雄,等.SRAM型FPGA单粒子效应逐位翻转故障注入方法[J].北京航空航天大学学报,2012,38(10):1285-1289 Song Ningfang,Qin Jiaomei,Pan Xiong,et al.Evaluating SEU effects in SRAM-based FPGA with bit-by-bit upset fault injection[J].Journal of Beijing University of Aeronautics and Astronautics,2012,38(10):1285-1289(in Chinese) [9] Maheshwari A,Koren I,Burleson W.Techniques for transient fault sensitivity analysis and reduction in VLSI circuits //Martin D C.Proceedings of the IEEE International Symposium on Defect and Fault-tolerance.Los Alamitos:IEEE Computer Society,2003:597-604 [10] Baraza J C,Gracia J,Gil D,et al.Improvement of fault injection techniques based on VHDL code modification //Harris I G.IEEE International High-Level Design Validation and Test Workshop.Los Alamitos:IEEE Computer Society,2005:19-26 [11] Ceschia M,Violante M,Reorda M S,et al.Identification and classification of single-event upsets in the configuration memory of sram-based fpgas[J].IEEE Transactions on Nuclear Science,2003,50(6):2088-2094 [12] 邢克飞.星载信号处理平台单粒子效应检测与加固技术研究 .长沙:国防科学技术大学,2007 Xing Kefei.Single event effect detection and mitigation techniques for spaceborne singal processing platform .Changsha:National University of Defense Technology,2007(in Chinese) [13] Mohanram K,Touba N A.Cost-effective approach for reducing soft error failure rate in logic circuits //Ambler A.Proceedings of International Test Conference.Los Alamitos:IEEE Computer Society,2003:893-901 [14] Liu B.Signal probability based statistical timing analysis // Preas K.Proceedings of IEEE Design,Automation and Test in Europe.Los Alamitos:IEEE Computer Society,2008:562-567 [15] Kehl N,Rosenstiel W.An efficent SER estimation method for combinational circuits[J].IEEE Transaction on Reliability,2011,60(4):742-747 [16] Monson J S,Wirthlin M J,Hutchings B L.Fault injection results of Linux operating on an FPGA embedded platform //Prasanna V.Proceedings of International Conference on Reconfigurable Computing and FPGAs.Los Alamitos:IEEE Computer Society,2010:37-42 [17] Yui C,Swift G,Carmichael C.SEU mitigation testing of the XILINX Virtex II FPGAs ///Wert J L.IEEE Radiation Effects Data Workshop.Piscataway:IEEE,2003:92-97
点击查看大图
计量
- 文章访问数: 2085
- HTML全文浏览量: 266
- PDF下载量: 517
- 被引次数: 0